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| may 2001 specifications subject to change with out notice,contact your sales representat ives for the most recent information. 1/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/80952 product list SM8051l25, 25 mhz 4kb internal rom mcu sm8052l25, 25 mhz 8kb internal rom mcu SM8051c25, 25 mhz 4kb internal rom mcu sm8052c25, 25 mhz 8kb internal rom mcu SM8051c40, 40 mhz 4kb internal rom mcu sm8052c40, 40 mhz 8kb internal rom mcu description the SM8051/8052 series product is an 8 - bit single chip micro controller with 4/8 kb rom embedded. it provides hardware features and a powerful instruction set, necessary to make it a versatile and cost effective controller for those applications demand up to 32 i/o pins or need up to 4/8 kb rom memory either for program or for data or mixed. ordering information yywwv SM8051/8052ihhk yy: year, ww:month v: version identifier { , a, b, ...} i: process identifier {l=3.0v ~ 3.6v, c=4.5v ~ 5.5v} hh: working clock in mhz {25, 40} k: package type postfix {as below table} features working voltage: 3.0v ~ 3.6v for l version 4.5v ~ 5.5v for c version general 8051/8052 family compatible 12 clocks per machine cycle 4/8 kb internal rom memory 128/256 bytes data ram 2/3 16 bit timers/counters four 8-bit i/o ports full duplex serial channel bit operation instruction page free jumps 8-bit unsigned division 8-bit unsigned multiply bcd arithmetic direct addressing indirect addressing nested interrupt two priority level interrupt a serial i/o port power save modes: idle mode and power down mode code protection function one watch dog timer (wdt) low emi (inhibit ale) postfix package pin/pad configuration dimension p 40l pdip page 2 page 13 j 44l plcc page 2 page 14 q 44l qfp/tqfp page 2 page 15/16 with 4/8kb rom embedded 8 - bit micro-controller ta i w a n 4f, no. 1 creation road 1, science-based industrial park, hsinchu, taiwan 30077 tel: 886-3-579-2926 fax: 886-3-579-2960 886-3-578-0493 886-3-579-2988
may 2001 specifications subject to change with out notice,contact your sales representat ives for the most recent information. 2/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/80952 pin configurations SM8051/8052ihhp (top view) 40l pdip vdd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 #ea ale #psen p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 res rxd/p3.0 txd/p3.1 #int/p3.2 #int1/p3.3 t0/p3.4 t1/p3.5 #wr/p3.6 #rd/p3.7 xtal1 xtal2 vss 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 10 40 39 38 37 36 35 34 33 32 31 30 28 27 26 25 24 23 22 21 29 p1.4 p1.3 p1.2 p1.1 p1.0 nc vdd p0.0/ad0 p0.2/ad2 p0.3/ad3 p0.1/ad1 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 #ea nc ale #psen p2.7/a15 p2.6/a14 p2.5/a13 p1.5 p1.6 p1.7 res rxd/p3.0 nc txd/p3.1 #int0/p3.2 #int1/p3.3 t0/p3.4 t1/p3.5 #wr/p3.6 #rd/p3.7 xtal2 xtal1 vss nc a8/p2.0 a9/p2.1 a10/p2.2 a11/p2.3 a12/p2.4 SM8051/8052 44l plcc (top view) 6 5 4 3 2 14443 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 ihhj ad3/p0.3 ad2/p0.2 ad1/p0.1 ad0/p0.0 vdd nc p1.0 p1.1 p1.2 p1.3 p1.4 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 nc vss xal1 xal2 p3.7/#rd p3.6/#wr p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 #ea nc ale #psen p2.7/a15 p2.6/a14 p2.5/a13 p1.5 p1.6 p1.7 res rxd/p3.0 nc txd/p3.1 #int0/p3.2 #int1/p3.3 t0/p3.4 t1/p3.5 SM8051/8052 44l qfp (top view) 33 32 31 30 27 26 25 24 23 29 28 22 21 20 18 17 16 15 14 13 19 12 11 10 9 8 7 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 inhq may 2001 specifications subject to change with out notice,contact your sales representat ives for the most recent information. 3/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/80952 timer 2 timer 1 timer 0 stack pointer decoder & register 128/256 bytes ram block diagram reset circuit power circuit interrupt circuit timing generator xtal2 xtal1 #ea ale #psen res vdd vss to pertinent blocks to whole chip to pertinent blocks to whole system acc buffer2 buffer1 alu psw buffer dptr pc incrementer program counter register 4/8 k bytes rom memory port 0 latch port 1 latch port 2 latch port 3 latch port 0 driver & mux port 1 driver & mux port 2 driver & mux port 3 driver & mux 8 8 8 8 wdt instruction register may 2001 specifications subject to change with out notice,contact your sales representat ives for the most recent information. 4/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/80952 pin descriptions 40l pdip pin# 44l qfp pin# 44l plcc pin# symbol active i/o names 1 40 2 p1.0 i/o bit 0 of port 1 2 41 3 p1.1 i/o bit 1 of port 1 3 42 4 p1.2 i/o bit 2 of port 1 4 43 5 p1.3 i/o bit 3 of port 1 5 44 6 p1.4 i/o bit 4 of port 1 6 1 7 p1.5 i/o bit 5 of port 1 7 2 8 p1.6 i/o bit 6 of port 1 8 3 9 p1.7 i/o bit 7 of port 1 9 4 10 res h i reset 10 5 11 rxd/p3.0 i/o receive data & bit 0 of port 3 11 7 13 txd/p3.1 i/o transmit data & bit 1 of port 3 12 8 14 #int0/p3.2 l/ - i/o low true interrupt 0 & bit 2 of port 3 13 9 15 #int1/p3.3 l/ - i/o low true interrupt 1 & bit 3 of port 3 14 10 16 t0/p3.4 i/o timer 0 & bit 4 of port 3 15 11 17 t1/p3.5 i/o timer 1 & bit 5 of port 3 16 12 18 #wr/p3.6 l/ - i/o external memory write & bit 6 of port 3 17 13 19 #rd/p3.7 l/ - i/o external memory read & bit 7 of port 3 18 14 20 xtal2 o crystal out 19 15 21 xtal1 i crystal in 20 16 22 vss sink voltage, ground 21 18 24 p2.0/a8 i/o bit 0 of port 2 & bit 8 of external memory address 22 19 25 p2.1/a9 i/o bit 1 of port 2 & bit 9 of external memory address 23 20 26 p2.2/a10 i/o bit 2 of port 2 & bit 10 of external memory address 24 21 27 p2.3/a11 i/o bit 3 of port 2 & bit 11 of external memory address 25 22 28 p2.4/a12 i/o bit 4 of port 2 & bit 12 of external memory address 26 23 29 p2.5/a13 i/o bit 5 of port 2 & bit 13 of external memory address 27 24 30 p2.6/a14 i/o bit 6 of port 2 & bit 14 of external memory address 28 25 31 p2.7/a15 i/o bit 7 of port 2 & bit 15 of external memory address 29 26 32 #psen l o program storage enable 30 27 33 ale - o address latch enable 31 29 35 #ea l i external access 32 30 36 p0.7/ad7 i/o bit 7 of port 0 & data/address bit 7 of external memory 33 31 37 p0.6/ad6 i/o bit 6 of port 0 & data/address bit 6 of external memory 34 32 38 p0.5/ad5 i/o bit 5 of port 0 & data/address bit 5 of external memory 35 33 39 p0.4/ad4 i/o bit 4 of port 0 & data/address bit 4 of external memory 36 34 40 p0.3/ad3 i/o bit 3 of port 0 & data/address bit 3 of external memory 37 35 41 p0.2/ad2 i/o bit 2 of port 0 & data/address bit 2 of external memory 38 36 42 p0.1/ad1 i/o bit 1 of port 0 & data/address bit 1 of external memory 39 37 43 p0.0/ad0 i/o bit 0 of port 0 & data/address bit 0 of external memory 40 38 44 vdd drive voltage, +5 vcc may 2001 specifications subject to change without notice,contact yo ur sales representatives for the most recent information. 5/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/8052 b acc psw t2con rc2l rc2h tl2 th2 ip sconf p3 ie p2 scon sbuf wdtc p1 tcon tmod tl0 tl1 th0 th1 p0 sp dpl dph (reserved) pcon sfr memory map $f8 $f0 $e8 $e0 $d8 $d0 $c8 $c0 $b8 $b0 $a8 $a0 $98 $90 $88 $80 $ff $f7 $ef $e7 $df $d7 $cf $c7 $bf $b7 $af $a7 $9f $97 $8f $87 note: the text of sfrs with bold type characters are extension special function registers for SM8051/8052 extension function description watch dog timer the watch dog timer (wdt) is a 16-bit free-running counter th at generate reset signal if t he counter overflows. the wdt is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. the wdt function can help user software re cover form abnormal software condition. the wdt is different from timer0, timer1 and timer2 of general 8052. to prevent a wdt reset can be done by software periodically clearing the wdt counter. the SM8051/8052 wdt has selectable divider input for the time base source clock. to select the divider input, the setting of bit2~bit0 (ps2~ps0) of watch dog timer control register (wdtc) should be se t accordingly. to enable the wdt is done by setting 1 to the bit 7 (wdte) of wdtc. after wdte set to 1, the 16-bit counter starts to count with the selected time base source clock which set by ps2~ps0. it will generat e a reset signal when overflows. the wdte bit will be cleared to 0 automatically when SM8051/ 8052 been reset, either hardware reset or wdt reset. to reset the wdt is done by setting 1 to the bit 5 (clear) of wdtc. this will clear th e content of the 16-bit counter and let the counter re-sta rt to count from the beginning. may 2001 specifications subject to change without notice,contact yo ur sales representatives for the most recent information. 6/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/8052 watch dog timer registers - wdt control register (wdtc, $9f) wdte : watch dog timer enable bit clear : watch dog timer reset bit ps2 ~ ps0 : clock source divider bit ps [2:0] di vider (osc in) time period (ms) @40mhz 000 8 13.1 001 16 26.21 010 32 52.42 011 64 104.8 100 128 209.71 101 256 419.43 110 512 838.86 111 1024 1677.72 watch dog timer register - system control register (sconf, $bf) the bit 7(wdr) of sconf is watch dog timer reset bi t. it will be set to 1 when reset signal generated by wdt overflow. user should check wdr bit whenever un-predicted reset happened. reduce emi function the SM8051/8052 allows user to reduce the emi emission by setting 1 to the bit 0 (alei) of sconf register. this function will inhibit the clock signal in fosc/6hz output to the ale pin. this function is available when there is no external program memory or no external data ram in the system. wdte unused clear unused unused ps2 ps1 ps0 0 * 0 * * 0 0 0 wdr unused unused unused unused unused unused alei 0 * * * * * * 0 reset value msb lsb reset value msb lsb wdr : watch dog timer reset. when system reset by watch dog timer overflow, wdr will be set to 1 alei : ale output inhibi t bit, to reduce emi may 2001 specifications subject to change with out notice,contact your sales representat ives for the most recent information. 7/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/80952 operating conditions symbol description min. typ. max. unit. remarks ta operating temperature 0 25 70 o c ambient temperature under bias ts storage temperature -55 25 155 o c vcc5 supply voltage 4.5 5.0 5.5 v for c version vcc3 supply voltage 3 3.3 3.6 v for l version fosc 25 oscillator frequency 3.0 25 25 mhz for 5v, 3.3v application fosc 40 oscillator frequency 3.0 40 40 mhz for 5v application symbol parameter valid vil1 input low voltage port 0,1,2,3,4,#ea vil2 input low voltage res, xtal1 vih1 input high voltage port 0,1,2,3,4,#ea vih2 input high voltage res, xtal1 vol1 output low voltage port 0, ale, #psen vol2 output low voltage port 1,2,3,4 voh1 output high voltage port 0 voh2 output high volt age port 1, 2,3,4,ale,#psen iil logical 0 input current port 1,2,3,4 itl logical transition current port 1,2,3,4 ili input leakage current port 0, #ea r res reset pulldown resistance res c io pin capacitance i cc power supply current vdd dc characteristics (12mhz, typical operating conditions, valid for SM8051/8052 series) + min. max. unit test conditions -0.5 0 2.0 70%vcc 2.4 90%vcc 50 2.4 90%vcc 0.8 0.8 vcc+0.5 vcc+0.5 0.45 0.45 -75 -650 10 300 10 7 4.5 10 v v v v v v v v v v ua ua ua kohm pf ma ma ua iol=8ma (5v) / iol=6ma (3.3v) iol=6.5ma (5v) / iol=6ma (3.3v) ioh=-800ua (only for vcc=5v) ioh=-80ua ioh=-60ua (only for vcc=5v) ioh=-10ua vin=0.45v vin=2.0v 0.45v may 2001 specifications subject to change with out notice,contact your sales representat ives for the most recent information. 9/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/80952 data memory read cycle timing osc t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 t3 ale 1 2 #psen #rd port2 port0 5 7 address a15 - a8 inst in float a7 - a0 3 4 3 float 6 data in 8 float address or float application reference x'tal 3mhz 6mhz 9mhz 12mhz c1 30 pf 30 pf 30 pf 30 pf c2 30 pf 30 pf 30 pf 30 pf r open open open open x'tal 16mhz 25mhz 33mhz 40mhz c1 30 pf 15 pf 10 pf 5 pf c2 30 pf 15 pf 10 pf 5 pf r open 62k ? 6.8k ? 4.7k ? note: oscillation circuit may differ s with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics. user should check with the crystal or ceramic resonator manufacturer for appropriate value of external components. xi x2 SM8051/8052 x'tal r c1 c2 valid for SM8051/8052 may 2001 specifications subject to change with out notice,contact your sales representat ives for the most recent information. 10/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/80952 osc ale #psen #rd,#wr port2 port0 t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 1 2 5 7 3 3 4 68 address a15 - a8 address a15 - a8 float a7 - a0 float inst in float a7 - a0 float inst in float program memory read cycle timing data memory write cycle timing osc t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t1 t2 ale 1 #psen #wr port2 port0 5 address a15 - a8 inst float a7 - a0 2 2 3 data out address or float 6 4 t12 t3 may 2001 specifications subject to change with out notice,contact your sales representat ives for the most recent information. 11/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/80952 i/o ports timing t6 t7 t8 t9 t10 t11 t12 t1 t2 t3 t4 t5 t6 t7 t8 inputs p0,p1 sampled sampled inputs p2,p3 output by mov px,src rxd at serial port shift clock (mode 0) current data next data sampled x1 timing critical, requirement of exte rnal clock (vss=0.0v is assumed) vdd-0.5v 0.45v 70%vdd 20%vdd-0.1v tchcl tclcl tchcx tclch tclcx tm.i external program memory read cycle #psen ale port 0 port 2 tplph tlhll tllpl tavll tllax tpxix tpxiz taviv tplaz tpliv a0 - a7 instruction. in a0 - a7 a8 - a15 a8 - a15 may 2001 specifications subject to change with out notice,contact your sales representat ives for the most recent information. 12/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/80952 tm.ii external data memory read cycle #psen ale #rd port 0 port 2 tyhlh tlldv tllyl trlrh tavll tllax trlaz tavyl tavdv p2.0 - p2.7 or a8 - a15 from dph trhdz trhdx a0 - a7 from ri or dpl data in a0 - a7 from pcl instrl in a8 - a15 from pch trldv tm.iii external da ta memory write cycle #psen ale #wr port 0 port 2 tlhll tyhlh tavll tllax tqvwx tllyl tavyl twlwh twhqx tqvwh a0-a7 from pcl instrl in p2.0-p2.7 or a8-a15 from dph a8-a15 from pch a0-a7 from ri or dpl data out may 2001 specifications subject to change with out notice,contact your sales representat ives for the most recent information. 13/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/80952 40l 600mil pdip information a1 e1 b1 b l a a2 d s ea c a e1 e note: 1. dimension d max & include mold flash or tie bar 2. dimension e1 does not include inter lead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 4. dimension b1 does not include dam bar protrusion/ 5. controlling dimension is inch. 6. general appearance spec. should base on final visual symbol dimension in inch minimal/maximal dimension in mm minimal/maximal a - / 0.210 - / 5.33 a1 0.010 / - 0.25 / - a2 0.150 / 0.160 3.81 / 4.06 b 0.016 / 0.022 0.41 / 0.56 b1 0.048 / 0.054 1.22 / 1.37 c 0.008 / 0.014 0.20 / 0.36 d - / 2.070 - / 52.58 e 0.590 / 0.610 14.99 / 15.49 e1 0.540 / 0.552 13.72 / 14.02 e1 0.090 / 0.110 2.29 / 2.79 l 0.120 / 0.140 3.05 / 3.56 a 0 / 15 0 / 15 ea 0.630 / 0.670 16.00 / 17.02 s - / 0.090 - / 2.29 burrs. infusion. inspection spec. may 2001 specifications subject to change with out notice,contact your sales representat ives for the most recent information. 14/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/80952 symbol dimension in inch minimal/maximal dimension in mm minimal/maximal a - / 0.185 - / 4.70 a1 0.020 / - 0.51 / - a2 0.145 / 0.155 3.68 / 3.94 b1 0.026 / 0.032 0.66 / 0.81 b 0.016 / 0.022 0.41 / 0.56 c 0.008 / 0.014 0.20 / 0.36 d 0.648 / 0.658 16.46 / 16.71 e 0.648 / 0.658 16.46 / 16.71 e 0.050 bsc 1.27 bsc gd 0.590 / 0.630 14.99 / 16.00 ge 0.590 / 0.630 14.99 / 16.00 hd 0.680 / 0.700 17.27 / 17.78 he 0.680 / 0.700 17.27 / 17.78 l 0.090 / 0.110 2.29 / 2.79 - / 0.004 - / 0.10 / / 44l plastic chip carrier (plcc) ehe d hd 6 7 note: 1. dimension d & e does not include inter lead flash. 2. dimension b1 does not include dam bar protrusion/ intrusion. 3. controlling dimension: inch 4. general appearance spec. should base on final visual inspection spec. y l y ge a2 a a1 e b1 b c gd may 2001 specifications subject to change with out notice,contact your sales representat ives for the most recent information. 15/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/80952 44l plastic quad flat package e2 e1 e d2 d1 d e1 e seating plane l1 l c s e b a2 a1 a 2 3 r1 r2 gage plane 0.25 mm note: dimension d1 and e1 do not include mold protrusion. allowance protrusion is 0.25mm per side. dimension d1 and e1 do include mold mismatch and are determined datum plane. dimension b does not include dam bar protrusion. allowance dam bar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dam bar cannot be located on the lower radius or the lead foot. symbol dimension in inch minimal/maximal dimension in mm minimal/maximal a - / 0.100 - / 2.55 a1 0.006 / 0.014 0.15 / 0.35 a2 0.071 / 0.087 1.80 / 2.20 b 0.012 / 0.018 0.30 / 0.45 c 0.004 / 0.009 0.09 / 0.20 d 0.520 bsc 13.20 bsc d1 0.394 bsc 10.00 bsc d2 0.315 8.00 e 0.520 bsc 13.20 bsc e1 0.394 bsc 10.00 bsc e2 0.315 8.00 e 0.031 bsc 0.80 bsc l 0.029 / 0.041 0.73 / 1.03 l1 0.063 1.60 r1 0.005 / - 0.13 / - r2 0.005 / 0.012 0.13 / 0.30 s 0.008 / - 0.20 / - 0 / 7 as left 1 0 / - as left 2 10 ref as left 3 7 ref as left c 0.004 0.10 c may 2001 specifications subject to change without notice,contact yo ur sales representatives for the most recent information. 16/16 ver 1.1 SM8051/8052 07/2005 syncmos technologies inc. SM8051/8052 44l thin plastic quad flat package dimension in inch (ref) dimension in mm (base) symbol minimal/maximal minimal/maximal a 0.047 (max) 1.200 (max) a1 0.004 +/- 0.002 0.100 +/- 0.050 a2 0.039 +/- 0.002 1.000 +/- 0.050 b 0.012 (typ) 0.30 (typ) e1 0.472 +/- 0.004 12.000 +/- 0.100 e 0.394 +/- 0.004 10.000 +/- 0.100 e 0.031 (typ) 0.800 (typ) t 0.005 (typ) 0.127 (typ) y 0.003 (typ) 0.076 (typ) 0 ~ 7 0 ~ 7 l 0.024 +/- 0.006 0.600 +/- 0.150 l1 0.039 (ref) 1.000 (ref) |
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